The quantization scheme is implemented in Elements, a convolutional neural network accelerator architecture that supports variable weight bit precision as well as sparsity. We demonstrate its capabilities training several networks on various tasks such as classification, object detection, segmentation, and image generation. We present a neural network quantization algorithm based on a hardware-software co- design approach. It reaches a power efficiency of 3 TOP/s/W with a throughput of almost 0.5 TOP/s in 6.3 mm2. Nullhop’s novelty is its ability to skip all multiplications including a zero-valued activation.
We propose Nullhop, an accelerator pioneering the use of feature map sparsity, typical of convolutional neural networks, and quantization to boost the hardware capabilities. The outcome of this analysis indicates how the power-efficiency gain following the reduction of the bit precision is non-linear and how it saturates when using a precision of 16 bits. We first study how a standard 28 nm CMOS process performs in the context of deep learning accelerators design, giving special consideration to the power and area of circuits based on standard cells when reduced precision arithmetic and short SRAM memory words are used. In this thesis, we propose a set of innovations and tech- nologies belonging to one of the many research lines sparkled by such demand, focusing on energy-efficient hardware for convolutional neural networks. The achieved increase in accuracy created the demand for faster, more power-efficient hardware suited for deployment on edge devices. The growth in popularity of these algorithms has its root in the exponential increase of com- puting power available for their training consequent to the diffusion of GPUs. Over the last ten years, the rise of deep learning has redefined the state-of-the-art in many com- puter vision and natural language processing tasks, with applications ranging from automated personal assistants and social network filtering to self-driving cars and drug development.
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